1. Field
Embodiments of the invention relate generally to a nonvolatile semiconductor memory device.
2. Description of the Related Art
A collectively patterned three-dimensional multilayer memory is presented in order to increase the memory capacity of a nonvolatile semiconductor memory device (memory) (for example, refer to JP-A 2007-266143 (Kokai)). This method can collectively form a multilayer memory irrespective of the number of stacked layers and therefore can suppress the increase of cost.
In the collectively patterned three-dimensional multilayer memory, insulating films and electrode films (to form word lines) are alternately stacked to form a multilayer body and through holes are collectively formed in the multilayer body. Then, a charge storage layer (memory layer) is formed on the side face of the through hole and silicon is buried in the through hole to form a silicon pillar. A tunnel insulating film is provided between the charge storage layer and the silicon pillar, and a block insulating film is provided between the charge storage layer and the electrode film. Thereby, a memory cell made of, for example, a MONOS (metal oxide nitride oxide semiconductor) transistor is formed at the intersection of each electrode film and the silicon pillar.
In such a collectively patterned three-dimensional multilayer memory, the block insulating film, the charge storage layer, the tunnel insulating film, a channel silicon (to form the silicon pillar; for example, amorphous silicon) are formed in this order on the side wall of the electrode film inside the through hole. Therefore, the film-formation order is opposite to that of conventional planar MONOS memory, and in particular the state of the interface between the tunnel insulating film and the channel silicon is significantly different between both.
That is, whereas in the case of the planar type, an oxidized interface formed by thermal oxidation of the channel silicon is formed between the tunnel insulating film and the channel silicon; in the case of the collectively patterned three-dimensional multilayer memory, an interface made by only film-forming amorphous silicon for channel on the tunnel insulating film is formed. At such an interface as the latter made by only the film-formation, a large number of energy levels that easily become trap sites of charges such as dangling bonds are generated, which may have a bad effect on device operation and reliability.
For example, when holes are injected from the channel side toward the charge storage layer in data erasing, the holes are captured not only in the charge storage layer but also in traps at the channel interface. If the holes captured in traps at shallow energy levels near the channel interface are released, data retention characteristics at the time of erasing degrade. Likewise, in data writing, injected electrons are captured in traps at the channel interface; and if the electrons are released, data retention characteristics at the time of writing degrade.
Thus, peculiarly in the collectively patterned three-dimensional multilayer memory, traps easily occur near the channel interface and this may degrade data retention characteristics; and there is room for improvement.